/*
 * Copyright (c) 1997, Chris Csanady,
 *                     Iowa State University Research Foundation, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice unmodified, this list of conditions, and the following
 *    disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	$Id: if_yfgreg.h,v 3.1 1997/07/07 19:04:09 ccsanady Exp ccsanady $
 */

#define YFG_VENDORID_PKT_ENG	0x1000
#define YFG_DEVICEID_YELLOWFIN	0x0702

#define YFG_PCI_IOBA	0x10
#define YFG_PCI_MMBA	0x14

#define PCI_LATENCY_TIMER	0x0c

struct yfg_csr {
	volatile u_int32_t	TxControl;
	volatile u_int32_t	TxStatus;
	volatile u_int32_t		rsv;
	volatile u_int32_t	TxCmdPtr;
	volatile u_int32_t	TxIntSel;
	volatile u_int32_t	TxBranchSel;
	volatile u_int32_t	TxWaitSel;
	volatile u_int32_t		rsv2[9];
	volatile u_int32_t	RxControl;
	volatile u_int32_t	RxStatus;
	volatile u_int32_t		rsv3;
	volatile u_int32_t	RxCmdPtr;
	volatile u_int32_t	RxIntSel;
	volatile u_int32_t	RxBranchSel;
	volatile u_int32_t	RxWaitSel;
	volatile u_int32_t		rsv4[9];
	volatile u_int16_t	EventStatus;
	volatile u_int16_t	IntEnable;
	volatile u_int16_t	IntClear;
	volatile u_int16_t	IntStatus;
	volatile u_int32_t		rsv5;
	volatile u_int32_t	ChipRev;
	volatile u_int32_t	DMAControl;
	volatile u_int32_t		rsv6;
	volatile u_int32_t	MemTest0;
	volatile u_int16_t	MemTest1;
	volatile u_int8_t	GPReg;
	volatile u_int8_t	GPControl;
	volatile u_int16_t	Config;
	volatile u_int16_t	BBIFrameGap;
	volatile u_int16_t	NBBIFrameGap;
	volatile u_int16_t		xxx[5];
	volatile u_int32_t	Config2;
	volatile u_int32_t		rsv7;
	volatile u_int32_t	RxDepthMarkers;
	volatile u_int32_t	FlowControl;
	volatile u_int32_t		rsv8;
	volatile u_int32_t	MACTestReg1;
	volatile u_int32_t	MACTestConfig;
	volatile u_int32_t		rsv9;
	volatile u_int16_t	AddrFilterReg;
	volatile u_int16_t	StationAddr[3];
	volatile u_int16_t	HashTable[4];
	volatile u_int16_t		xxx2[2];
	volatile u_int16_t	PhyIdent[2];
	volatile u_int16_t		xxx3[4];
	volatile u_int8_t	EEStatus;
	volatile u_int8_t	EEControl;
	volatile u_int8_t	EEWordAddr;
	volatile u_int8_t	EEReadData;
	volatile u_int8_t	EEWriteData;
	volatile u_int8_t	EEFeatEnable;
	volatile u_int16_t		rsv10;
	volatile u_int16_t	ExtFifoConfig;
	volatile u_int16_t	ChipTestConfig;
};

/*
 * Set/unset bits in mask.  Mask is always left shifted 16 bits.
 */
#define SET_MASK(mask, bits)	((mask) << 16 | (bits))

/*
 * Channel control/status bits
 */
#define RUN		0x8000
#define PAUSE	0x4000
#define WAKE	0x1000
#define DEAD	0x0800
#define ACTIVE	0x0400
#define BT		0x0100
#define TXABORT	0x0080		/* Tx only */
#define TXSR	0x0040		/* Tx only */
#define EOP		0x0040		/* Rx only */

/*
 * DMA register bits
 */
#define DMA_SRST	0x80000000
#define DMA_TDPCE	0x00800000
#define DMA_BE		0x00400000
#define DMA_DPMRLE	0x00008000
#define DMA_WIE		0x00004000
#define DMA_DDPE	0x00000400
#define DMA_TDPE	0x00080000

/*
 * Config register bits
 */
#define SRST	0x8000
#define RXEN	0x1000
#define STRIP	0x0080
#define SIFT	0x0040
#define PARF	0x0020
#define FLCHK	0x0010
#define CRCEN	0x0008
#define PADEN	0x0004
#define FULLD	0x0002
#define CRCE	0x0001
#define PHY_10B	0x0100

/*
 * Interrupt register bits
 */
#define INT_EN		0x8000
#define INT_WI		0x0200
#define INT_ERI		0x0100
#define INT_PPET	0x0080
#define INT_PBFT	0x0040
#define INT_IIDT	0x0020
#define INT_DIT		0x0010
#define INT_PPER	0x0008
#define INT_PBFR	0x0004
#define INT_IIDR	0x0002
#define INT_DIR		0x0001
#define INT_ALL		0x01FF

/*
 * Flow control
 */
#define FC_TX		0x00200000
#define FC_RX		0x00100000

/*
 * Command descriptor format
 */
struct yfg_desc {
	volatile u_int16_t	reqCount;
	volatile u_int16_t	cmd;
	volatile u_int32_t	addr;
	volatile u_int32_t	baddr;
	volatile u_int16_t	resCount;
	volatile u_int16_t	xferStatus;
};
#define CMD_OUT_MORE	0x0000
#define CMD_OUT_LAST	0x1000
#define CMD_IN_MORE		0x2000
#define CMD_IN_LAST		0x3000
#define CMD_NOP			0x6000
#define CMD_STOP		0x7000
#define WAIT_TRUE		0x0001
#define WAIT_FALSE		0x0002
#define WAIT_ALWAYS		0x0003
#define BRAN_TRUE		0x0004
#define BRAN_FALSE		0x0008
#define BRAN_ALWAYS		0x000C
#define INT_TRUE		0x0010
#define INT_FALSE		0x0020
#define INT_ALWAYS		0x0030

/*
 * Frame statistics block
 */
struct yfg_status {
	u_int16_t	count;
	u_int16_t	status;
	u_int16_t	total;
	u_int16_t	pause;
};
#define FRAME_OK	0x80

/*
 * Tx control block.  Must be 2^n in size, with the
 * descriptors aligned to 16 bytes.
 */
#define YFG_NTXSEG 7
struct yfg_tx_cb {
	struct yfg_status frame;
	struct mbuf *mb_head;
	struct yfg_tx_cb *next;
	struct yfg_desc tdb[YFG_NTXSEG];
};

struct yfg_rx_cb {
	struct yfg_rx_cb *next;
	struct yfg_desc *desc;
};