/dev/pmc: version 1.10, compiled for Pentium II, Linux kernel 2.0.36 processor: cache is enabled rdtsc is enabled rdpmc is enabled system alignment checking is enabled local APIC: this is the bootstrap processor the local APIC is enabled, base address = 0x0:fee00000 PMC read tests read PMC_READ_CR0 0x80050033 read PMC_READ_CR2 0x4009dd5d read PMC_READ_CR3 0x0d407000 read PMC_READ_CR4 0x00000110 read PMC_READ_CONTROL_0 0x0000000000000000 read PMC_READ_CONTROL_1 0x0000000000000000 read PMC_READ_TSC 0x000571f1a14f0cca read PMC_READ_0 0x00057100024fb696 read PMC_READ_1 0x0005710000000000 read PMC_READ 0x000571f1a14f2ff8 0x00000000024fb696 0x0000000000000000 read PMC_READ_CONTROL 0x0000000000000000 0x0000000000000000 PMC write tests write PMC_WRITE_0 0x0000000012345678 write PMC_WRITE_1 0x0000000012345678 read PMC_READ_TSC 0x000571f1a152b75a read PMC_READ_0 0x0005710012345678 read PMC_READ_1 0x0005710012345678 write PMC_WRITE_0 0x0000000087654321 write PMC_WRITE_1 0x0000000087654321 read PMC_READ_TSC 0x000571f1a152f7b8 read PMC_READ_0 0x000571ff87654321 read PMC_READ_1 0x000571ff87654321 write PMC_WRITE_0 0x8765432112345678 write PMC_WRITE_1 0x8765432112345678 read PMC_READ_TSC 0x000571f1a153321d read PMC_READ_0 0x0005710012345678 read PMC_READ_1 0x0005710012345678 write PMC_WRITE_0 0x1234567887654321 write PMC_WRITE_1 0x1234567887654321 read PMC_READ_TSC 0x000571f1a153c5f9 read PMC_READ_0 0x000571ff87654321 read PMC_READ_1 0x000571ff87654321 write PMC_WRITE_0 0xffffffffffffffff write PMC_WRITE_1 0xffffffffffffffff read PMC_READ_TSC 0x000571f1a156fa8c read PMC_READ_0 0x000571ffffffffff read PMC_READ_1 0x000571ffffffffff write PMC_WRITE_0 0x0000000000000000 write PMC_WRITE_1 0x0000000000000000 read PMC_READ_TSC 0x000571f1a15741b3 read PMC_READ_0 0x0005710000000000 read PMC_READ_1 0x0005710000000000 PMC control write tests write PMC_WRITE_CONTROL_0 0x0000000012345678 write PMC_WRITE_CONTROL_1 0x0000000012345678 read PMC_READ_TSC 0x000571f1a1578160 read PMC_READ_CONTROL_0 0x0000000012345678 read PMC_READ_CONTROL_1 0x0000000012345678 write PMC_WRITE_CONTROL_0 0x0000000087654321 write PMC_WRITE_CONTROL_1 0x0000000087654321 read PMC_READ_TSC 0x000571f1a157bd43 read PMC_READ_CONTROL_0 0x0000000087654321 read PMC_READ_CONTROL_1 0x0000000087654321 write PMC_WRITE_CONTROL_0 0x8765432112345678 write PMC_WRITE_CONTROL_1 0x8765432112345678 read PMC_READ_TSC 0x000571f1a157f8d1 read PMC_READ_CONTROL_0 0x0000000012345678 read PMC_READ_CONTROL_1 0x0000000012345678 write PMC_WRITE_CONTROL_0 0x1234567887654321 write PMC_WRITE_CONTROL_1 0x1234567887654321 read PMC_READ_TSC 0x000571f1a15b400c read PMC_READ_CONTROL_0 0x0000000087654321 read PMC_READ_CONTROL_1 0x0000000087654321 write PMC_WRITE_CONTROL_0 0xffffffffffffffff write PMC_WRITE_CONTROL_1 0xffffffffffffffff read PMC_READ_TSC 0x000571f1a15b7c74 read PMC_READ_CONTROL_0 0x00000000ffffffff read PMC_READ_CONTROL_1 0x00000000ffffffff write PMC_WRITE_CONTROL_0 0x0000000000000000 write PMC_WRITE_CONTROL_1 0x0000000000000000 read PMC_READ_TSC 0x000571f1a15bb837 read PMC_READ_CONTROL_0 0x0000000000000000 read PMC_READ_CONTROL_1 0x0000000000000000 write PMC_WRITE_0 0x0000000000000000 write PMC_WRITE_1 0x0000000000000000 read PMC_READ_TSC 0x000571f1a15bf2f6 read PMC_READ_0 0x0005710000000000 read PMC_READ_1 0x0005710000000000 PMC timing tests, with measurement overhead subtracted cycles for overhead = 33 33 33 33 33 33 33 cycles for rdmsr = 72 72 72 72 72 72 72 cycles for rdmsr, wrmsr = 158 158 158 158 158 158 158 cycles for rdtsc = 33 33 33 33 33 33 33 cycles for rdpmc 0 = 31 31 31 31 31 31 31 cycles for rdpmc 1 = 31 31 31 31 31 31 31 cycles for rdtsc, rdpmc, rdpmc = 94 94 94 94 94 94 94 cycles for store and reload = 499 499 499 499 499 499 499