processor information:
  GenuineIntel Pentium Pro-class processor
  Original OEM (primary) processor
  P6 family, Pentium Pro, stepping 7
  Pentium Pro
  Cycle and event counters, access method
    rdtsc instruction from any CPL
    rdpmc instruction from any CPL
  Cache configuration
    L1 instr TLB, 4K page, 4-way, 32 entries
    L1 instr TLB, 4M page, fully associative, 2 entries
    L1 data  TLB, 4K page, 4-way, 64 entries
    L1 data  TLB, 4M page, 4-way,  8 entries
    L1 instr cache,  8 KB, 2- or 4-way (newer), 32 byte line
    L1 data  cache,  8 KB, 2-way, 32 byte line
    L2 cache, 256 KB, 4-way, 32 byte line
  Indicated features
     0 Floating Point Unit
     1 Virtual-8086 Mode Extension
     2 Debugging Extension
     3 Page Size Extension
     4 Time Stamp Counter
     5 Model Specific Registers
     6 Physical Address Extension
     7 Machine Check Exception
     8 CMPXCHG8B Instruction
    12 Memory Type Range Registers
    13 Page Global Enable
    14 Machine Check Architecture
    15 Conditional Move Instructions

/dev/pmc:
  version 1.10 for Pentium Pro, Linux kernel 2.2.13

rabbit:
  version 1.10 for Pentium Pro
  compiler options:
    -DPMC_P6 -DPMC_MHZ=200 -malign-double -DPMC_READ_SERIAL