#ifndef PMC_EVENTS_H #define PMC_EVENTS_H /*----------------------------------------------------------------------------*/ /* * Performance-Monitoring Counters Library, for Intel/AMD Processors and Linux * Author: Don Heller, dheller@scl.ameslab.gov * Last revised: 5 October 2001 * unfinished - P15 family is made to look like P6 family */ /*----------------------------------------------------------------------------*/ /* event codes */ /*----------------------------------------------------------------------------*/ #include /*----------------------------------------------------------------------------*/ /* event codes, using Intel's official names, * no matter that these names are inconsistent and * often incomprehensible without access to the manuals, * which are not always so helpful anyway */ /*----------------------------------------------------------------------------*/ #if defined(PMC_P5) #define PMC_EVENT_MAX 0x3F /* selector = 6 bits */ /* Pentium and Pentium with MMX */ /* DURATION: 18, 19, 1A, 1B, 1F */ #define DATA_READ 0x00 #define DATA_WRITE 0x01 #define DATA_TLB_MISS 0x02 #define DATA_READ_MISS 0x03 #define DATA_WRITE_MISS 0x04 #define DATA_WRITE_HIT_TO_M_OR_E_STATE_LINE 0x05 #define DATA_CACHE_LINES_WRITTEN_BACK 0x06 #define EXTERNAL_SNOOPS 0x07 #define EXTERNAL_DATA_CACHE_SNOOP_HITS 0x08 #define MEMORY_ACCESSES_IN_BOTH_PIPES 0x09 #define BANK_CONFLICTS 0x0A #define MISALIGNED_DATA_MEMORY_OR_IO_REFERENCES 0x0B #define CODE_READ 0x0C #define CODE_TLB_MISS 0x0D #define CODE_CACHE_MISS 0x0E #define ANY_SEGMENT_REGISTER_LOADED 0x0F #define SEGMENT_DESCRIPTOR_CACHE_ACCESS 0x10 #define SEGMENT_DESCRIPTOR_CACHE_HIT 0x11 #define BRANCHES 0x12 #define BTB_HITS 0x13 #define TAKEN_BRANCH_OR_BTB_HIT 0x14 #define PIPELINE_FLUSHES 0x15 #define INSTRUCTIONS_EXECUTED 0x16 #define INSTRUCTIONS_EXECUTED_V_PIPE 0x17 #define BUS_CYCLE_DURATION 0x18 #define WRITE_BUFFER_FULL_STALL_DURATION 0x19 #define WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION 0x1A #define WRITE_TO_AN_E_OR_M_STATE_LINE_STALL_DURATION 0x1B #define LOCKED_BUS_CYCLE 0x1C #define IO_READ_OR_WRITE_CYCLE 0x1D #define NONCACHEABLE_MEMORY_READS 0x1E #define PIPELINE_AGI_STALL_DURATION 0x1F #define SOURCE_DESTINATION_CONFLICTS 0x20 #define EVENT_0X21 0x21 #define FLOPS 0x22 #define BREAKPOINT_MATCH_ON_DR0_REGISTER 0x23 #define BREAKPOINT_MATCH_ON_DR1_REGISTER 0x24 #define BREAKPOINT_MATCH_ON_DR2_REGISTER 0x25 #define BREAKPOINT_MATCH_ON_DR3_REGISTER 0x26 #define HARDWARE_INTERRUPTS 0x27 #define DATA_READ_OR_WRITE 0x28 #define DATA_READ_MISS_OR_WRITE_MISS 0x29 #ifdef PMC_MMX /* Pentium with MMX only */ /* counter 0 only */ /* DURATION: 2A, 2E, 30, 32, 38, 3B */ #define BUS_OWNERSHIP_LATENCY 0x2A #define MMX_INSTRUCTIONS_EXECUTED_U_PIPE 0x2B #define CACHE_M_STATE_LINE_SHARING 0x2C #define EMMS_INSTRUCTIONS_EXECUTED 0x2D #define BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY 0x2E #define SATURATING_MMX_INSTRUCTIONS_EXECUTED 0x2F #define NUMBER_OF_CYCLES_NOT_IN_HALT_STATE 0x30 #define MMX_INSTRUCTION_DATA_READS 0x31 #define FLOATING_POINT_STALLS_DURATION 0x32 #define D1_STARVATION_AND_FIFO_IS_EMPTY 0x33 #define MMX_INSTRUCTION_DATA_WRITES 0x34 #define PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTION 0x35 #define MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS 0x36 #define MISPREDICTED_OR_UNPREDICTED_RETURNS 0x37 #define MMX_MULTIPLY_UNIT_INTERLOCK 0x38 #define RETURNS 0x39 #define BTB_FALSE_ENTRIES 0x3A #define FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS \ 0x3B /* Pentium with MMX only */ /* counter 1 only */ /* DURATION: 30, 36, 38, 3B */ #define BUS_OWNERSHIP_TRANSFERS 0x2A #define MMX_INSTRUCTIONS_EXECUTED_V_PIPE 0x2B #define CACHE_LINE_SHARING 0x2C #define TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS 0x2D #define WRITES_TO_NONCACHEABLE_MEMORY 0x2E #define SATURATIONS_PERFORMED 0x2F #define DATA_CACHE_TLB_MISS_STALL_DURATION 0x30 #define MMX_INSTRUCTION_DATA_READ_MISSES 0x31 #define TAKEN_BRANCHES 0x32 #define D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO 0x33 #define MMX_INSTRUCTION_DATA_WRITE_MISSES 0x34 #define PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTION_RESOLVED_IN_WB_STAGE \ 0x35 #define PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS 0x36 #define PREDICTED_RETURNS 0x37 #define MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION 0x38 #define EVENT_0X39_1 0x39 #define BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH 0x3A #define STALL_ON_MMX_INSTRUCTION_TO_E_OR_M_STATE_LINE 0x3B /* Pentium with MMX only */ /* undocumented */ #define EVENT_0X3C 0x3C #define EVENT_0X3D 0x3D #define EVENT_0X3E 0x3E #define EVENT_0X3F 0x3F #endif /* PMC_MMX */ #endif /* PMC_P5 */ /*----------------------------------------------------------------------------*/ #if defined(PMC_P6) || defined(PMC_P15) #define PMC_EVENT_MAX 0xFF /* selector = 8 bits */ /* Pentium Pro/II/III */ #define DATA_MEM_REFS 0x43 #define DCU_LINES_IN 0x45 #define DCU_M_LINES_IN 0x46 #define DCU_M_LINES_OUT 0x47 #define DCU_MISS_OUTSTANDING 0x48 #define IFU_IFETCH 0x80 #define IFU_IFETCH_MISS 0x81 #define ITLB_MISS 0x85 #define IFU_MEM_STALL 0x86 #define ILD_STALL 0x87 #define L2_IFETCH 0x28 #define L2_LD 0x29 #define L2_ST 0x2A #define L2_LINES_IN 0x24 #define L2_LINES_OUT 0x26 #define L2_M_LINES_INM 0x25 #define L2_M_LINES_OUTM 0x27 #define L2_RQSTS 0x2E #define L2_ADS 0x21 #define L2_DBUS_BUSY 0x22 #define L2_DBUS_BUSY_RD 0x23 #define BUS_DRDY_CLOCKS 0x62 #define BUS_LOCK_CLOCKS 0x63 #define BUS_REQ_OUTSTANDING 0x60 #define BUS_TRAN_BRD 0x65 #define BUS_TRAN_RFO 0x66 #define BUS_TRANS_WB 0x67 #define BUS_TRAN_IFETCH 0x68 #define BUS_TRAN_INVAL 0x69 #define BUS_TRAN_PWR 0x6A #define BUS_TRANS_P 0x6B #define BUS_TRANS_IO 0x6C #define BUS_TRAN_DEF 0x6D #define BUS_TRAN_BURST 0x6E #define BUS_TRAN_ANY 0x70 #define BUS_TRAN_MEM 0x6F #define BUS_DATA_RCV 0x64 #define BUS_BNR_DRV 0x61 #define BUS_HIT_DRV 0x7A #define BUS_HITM_DRV 0x7B #define BUS_SNOOP_STALL 0x7E #define FLOPS 0xC1 #define FP_COMP_OPS_EXE 0x10 #define FP_ASSIST 0x11 #define MUL 0x12 #define DIV 0x13 #define CYCLES_DIV_BUSY 0x14 #define LD_BLOCKS 0x03 #define SB_DRAINS 0x04 #define MISALIGN_MEM_REF 0x05 #define INST_RETIRED 0xC0 #define UOPS_RETIRED 0xC2 #define INST_DECODER 0xD0 #define HW_INT_RX 0xC8 #define CYCLES_INT_MASKED 0xC6 #define CYCLES_INT_PENDING_AND_MASKED 0xC7 #define BR_INST_RETIRED 0xC4 #define BR_MISS_PRED_RETIRED 0xC5 #define BR_TAKEN_RETIRED 0xC9 #define BR_MISS_PRED_TAKEN_RET 0xCA #define BR_INST_DECODED 0xE0 #define BTB_MISSES 0xE2 #define BR_BOGUS 0xE4 #define BACLEARS 0xE6 #define RESOURCE_STALLS 0xA2 #define PARTIAL_RAT_STALLS 0xD2 #define SEGMENT_REG_LOADS 0x06 #define CPU_CLK_UNHALTED 0x79 #ifdef PMC_MMX /* Pentium II/III only */ #define MMX_INSTR_EXEC 0xB0 #define MMX_SAT_INSTR_EXEC 0xB1 #define MMX_UOPS_EXEC 0xB2 #define MMX_INSTR_TYPE_EXEC 0xB3 #define FP_MMX_TRANS 0xCC #define MMX_ASSIST 0xCD #define MMX_INSTR_RET 0xCE #define SEG_RENAME_STALLS 0xD4 #define SEG_REG_RENAMES 0xD5 #define RET_SEG_RENAMES 0xD6 /* undocumented */ #define PII_0X52 0x52 #define PII_0XCF 0xCF #endif /* PMC_MMX */ #ifdef PMC_SSE /* Pentium III only */ #define EMON_SSE_INST_RETIRED 0xD8 #define EMON_SSE_COMP_INST_RET 0xD9 #define EMON_SSE_PRE_DISPATCHED 0x07 #define EMON_SSE_PRE_MISS 0x4B #endif /* PMC_SSE */ #ifdef PMC_SSE2 /* Pentium 4 only */ #endif /* PMC_SSE2 */ #endif /* PMC_P6 */ /*----------------------------------------------------------------------------*/ /* AMD Athlon */ /* the names are derived from AMD's description */ #if defined(PMC_K7) #define PMC_EVENT_MAX 0xFF /* selector = 8 bits */ #define L1_DATA_CACHE_ACCESSES 0x40 #define L1_DATA_CACHE_MISSES 0x41 #define L1_DATA_CACHE_REFILLS_FROM_L2 0x42 #define L1_DATA_CACHE_REFILLS_FROM_SYSTEM 0x43 #define L1_DATA_CACHE_WRITEBACKS 0x44 #define L1_DTLB_MISSES_AND_L2_DTLB_HITS 0x45 #define L1_AND_L2_DTLB_MISSES 0x46 #define MISALIGNED_DATA_REFERENCES 0x47 #define L1_INSTR_CACHE_FETCHES 0x80 #define L1_INSTR_CACHE_MISSES 0x81 #define L1_ITLB_MISSES_AND_L2_ITLB_HITS 0x84 #define L1_AND_L2_ITLB_MISSES 0x85 #define RETIRED_INSTRUCTIONS 0xC0 #define RETIRED_OPS 0xC1 #define RETIRED_BRANCHES 0xC2 #define RETIRED_BRANCHES_MISPREDICTED 0xC3 #define RETIRED_TAKEN_BRANCHES 0xC4 #define RETIRED_TAKEN_BRANCHES_MISPREDICTED 0xC5 #define RETIRED_FAR_CONTROL_TRANSFERS 0xC6 #define RETIRED_RESYNC_BRANCHES 0xC7 #define INTERRUPTS_MASKED_CYCLES 0xCD #define INTERRUPTS_MASKED_WHILE_PENDING_CYCLES 0xCE #define TAKEN_HARDWARE_INTERRUPTS 0xCF #endif /* PMC_K7 */ /*----------------------------------------------------------------------------*/ #endif /* PMC_EVENTS_H */