# rabbit, input file for Pentium Pro or Pentium II/III # event selection, replication factor and number of pairs # -number 1 # Pentium Pro # --event_pairs 128 # Pentium II --event_pairs 135 # Pentium III (for now, same as Pentium II) # --event_pairs 135 # Performance-Monitoring Counters # the columns are as follows: # event code (1 or 2 hex digits) # duration: count events (0) or cycles (1) # it is always 0 in this file # user mode: enable for CPL = 1,2,3 (1) or disable (0) # OS mode: enable for CPL = 0 (1) or disable (0) # unit mask (1 or 2 hex digits, depends on the event code) # comparison inversion flag (0 or 1) # comparison value (unsigned decimal integer) # event name (not used as input) # use the keyword -Label to supply descriptive text for the next event pair # Event Pairs # # x: event 0 per inst_retired (0xc0) # y: also, event 0 per cpu_clk_unhalted (0x79) # *: event 0 per event 1 # +: event 1 per event 0 (*-symmetry) # @: this processor and all bus agents # # row label is event 0, column label is event 1 # # # Instruction Access # # 80 81 85 86 87 28 68 # 80 y + + + + + + ifu_ifetch # 81 * x + + + ifu_ifetch_miss # 85 * * x + itlb_miss # 86 * * x + ifu_mem_stall # 87 * * ild_stall # 28 * * * x + l2_ifetch # 68 * * x bus_tran_ifetch # # # Data Access # # 43 45 46 47 48 29 2a 2e 22 23 24 26 25 27 21 60 62 # 43 y + + + + data_mem_refs # 45 * x * * + + * + dcu_lines_in # 46 * + x * * * dcu_m_lines_in # 47 * + + x * dcu_m_lines_out # 48 * y + dcu_miss_outstanding # 29 * * + x * * + l2_ld # 2a + x * l2_st # 2e + + x + + + + l2_rqsts # 22 * y + * l2_dbus_busy # 23 * * y l2_dbus_busy_rd # 24 + * x * * + l2_lines_in # 26 + * l2_lines_out # 25 + + * l2_m_lines_inm # 27 + + + l2_m_lines_outm # 21 * x l2_ads # 60 * * * * x bus_req_outstanding # 62 + x bus_drdy_clocks # # # Memory Ordering and Segment Registers # # 43 03 04 05 06 d4 d5 d6 # 43 y + + data_mem_refs # 03 * + ld_blocks # 04 * sb_drains # 05 * misalign_mem_ref # 06 x + segment_reg_loads # d4 * x seg_rename_stalls (PII) # d5 * seg_reg_renames (PII) # d6 + ret_seg_renames (PII) # # a2 d2 # a2 x resource_stalls # d2 x partial_rat_stalls # # # Data Bus Transactions # # 2e # 28 * instruction fetch # 29 * data load # 2a * data store # 2e x requests (all the above) # # # External Bus Transactions # # 6e 6b 6f 70 transaction type # 65 @ burst read # 66 @ read for ownership # 67 @ writeback # 68 @ instruction fetch # 6a @ partial write # 6e x @ burst # 6b x @ partial # 69 @ invalidate # 6c @ i/o # 6d @ deferred # 6f x @ memory # 70 x (all) # # # External Bus Transactions per L2 Miss # # 65 66 67 68 69 # 24 # 25 # 26 # 27 # # # External Bus Cycles # # 62 64 61 63 7a 7b 7e # 62 @ + + bus_drdy_clocks # 64 * * bus_data_rcv # 61 * + bus_bnr_drv # 63 @ bus_lock_clocks # 7a * bus_hit_drv # 7b + bus_hitm_drv # 7e y bus_snoop_stall # # # Decoding and Execution Units # # 80 d0 c0 c2 c1 # 80 y + ifu_ifetch # d0 * x * inst_decoder # c0 + y + + inst_retired # c2 * x uops_retired # c1 * y flops retired # # # 10 11 12 13 14 # 10 y * * * fp_comp_ops_exe # 11 + fp_assist # 12 + mul # 13 + + div # 14 * y cycles_div_busy # # # c6 c7 c8 # c6 * cycles_int_masked # c7 + cycles_int_pending_and_masked # c8 y hw_int_rx # # # d0 e0 e2 e4 e6 c4 c5 c9 ca # d0 x + * inst_decoder # e0 * + * br_inst_decoded # e2 * btb_misses # e4 * br_bogus # e6 + baclears # c4 + x + + + br_inst_retired # c5 + * x br_miss_pred_retired # c9 * br_taken_retired # ca * br_miss_pred_taken_ret # # # b0 b1 b2 b3 cc cd ce (Pentium II only) # b0 * MMX_instr_exec # b1 + MMX_sat_instr_exec # b2 * MMX_uops_exec # b3 + MMX_instr_type_exec # cc s fp_MMX_trans # cd * MMX_assist # ce + MMX_instr_ret # Round up the usual suspects ... -Label Cycles per instruction retired 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted 0xc0 0 1 1 0x0 0 0 inst_retired -Label Micro-operations retired per instruction retired 0xc2 0 1 1 0x0 0 0 uops_retired 0xc0 0 1 1 0x0 0 0 inst_retired -Label Flops per instruction retired 0xc1 0 1 1 0x0 0 0 flops 0xc0 0 1 1 0x0 0 0 inst_retired -Label Flops per cycle and per sec. 0xc1 0 1 1 0x0 0 0 flops 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label Speculative execution factor 0xd0 0 1 1 0x0 0 0 inst_decoder 0xc0 0 1 1 0x0 0 0 inst_retired -Label Resource stalls per instruction retired 0xa2 0 1 1 0x0 0 0 resource_stalls 0xc0 0 1 1 0x0 0 0 inst_retired # Instruction Fetch Unit # events 0x80, 0x81, 0x85, 0x86, 0x87 # # Instruction Decode and Retire Unit # events 0xd0, 0xc0, 0xc2 -Label Instruction fetches per active cycle 0x80 0 1 1 0x0 0 0 ifu_ifetch 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label Speculative execution: Instruction fetches per instruction retired 0x80 0 1 1 0x0 0 0 ifu_ifetch 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 instruction-cache misses per instruction retired 0x81 0 1 1 0x0 0 0 ifu_ifetch_miss 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 instruction-TLB misses per instruction retired 0x85 0 1 1 0x0 0 0 itlb_miss 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 instruction-stall cycles per instruction retired 0x86 0 1 1 0x0 0 0 ifu_mem_stall 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 instruction-cache miss ratio (per instruction fetch) 0x81 0 1 1 0x0 0 0 ifu_ifetch_miss 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label L1 instruction-cache TLB miss ratio (per instruction fetch) 0x85 0 1 1 0x0 0 0 itlb_miss 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label L1 instruction-cache TLB miss ratio (per instruction fetch miss) 0x85 0 1 1 0x0 0 0 itlb_miss 0x81 0 1 1 0x0 0 0 ifu_ifetch_miss -Label L1 instruction-stall cycles per instruction fetch 0x86 0 1 1 0x0 0 0 ifu_mem_stall 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label Instructions decoded per instruction fetch 0xd0 0 1 1 0x0 0 0 inst_decoder 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label L1 instruction length decoder, stall cycles per instruction fetch 0x87 0 1 1 0x0 0 0 ild_stall 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label L1 instruction-cache miss penalty, cycles per instruction fetch miss 0x86 0 1 1 0x0 0 0 ifu_mem_stall 0x81 0 1 1 0x0 0 0 ifu_ifetch_miss -Label L1 instruction-cache stall propagation (fetch to decode) 0x87 0 1 1 0x0 0 0 ild_stall 0x86 0 1 1 0x0 0 0 ifu_mem_stall # Data Cache Unit # events 0x43, 0x45, 0x46, 0x47, 0x48 -Label Data references per active cycle # includes speculative loads for instructions executed but not retired 0x43 0 1 1 0x0 0 0 data_mem_refs 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label Data references per instruction retired # includes speculative loads for instructions executed but not retired 0x43 0 1 1 0x0 0 0 data_mem_refs 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 data-cache misses per instruction retired # includes speculative loads for instructions executed but not retired 0x45 0 1 1 0x0 0 0 dcu_lines_in 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 data-cache store misses per instruction retired # includes speculative loads for ownership for instructions executed # but not retired; there are no speculative stores 0x46 0 1 1 0x0 0 0 dcu_m_lines_in 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 data-cache evictions per instruction retired 0x47 0 1 1 0x0 0 0 dcu_m_lines_out 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 data-cache miss ratio (lines in / data reference) # includes speculative loads for instructions executed but not retired 0x45 0 1 1 0x0 0 0 dcu_lines_in 0x43 0 1 1 0x0 0 0 data_mem_refs -Label L1 data-cache store miss ratio (modified lines in / data reference) 0x46 0 1 1 0x0 0 0 dcu_m_lines_in 0x43 0 1 1 0x0 0 0 data_mem_refs -Label L1 data-cache eviction ratio (modified lines out / data reference) 0x47 0 1 1 0x0 0 0 dcu_m_lines_out 0x43 0 1 1 0x0 0 0 data_mem_refs -Label L1 data-cache aggregate miss penalty (cycles) (inaccurate) 0x48 0 1 1 0x0 0 0 dcu_miss_outstanding 0x45 0 1 1 0x0 0 0 dcu_lines_in -Label Average number of unsatisfied references pending per cycle (inaccurate) 0x48 0 1 1 0x0 0 0 dcu_miss_outstanding 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label L1 data-cache traffic ratio (lines in / modified lines in) 0x45 0 1 1 0x0 0 0 dcu_lines_in 0x46 0 1 1 0x0 0 0 dcu_m_lines_in -Label L1 data-cache traffic ratio (lines in / modified lines out) 0x45 0 1 1 0x0 0 0 dcu_lines_in 0x47 0 1 1 0x0 0 0 dcu_m_lines_out -Label L1 data-cache traffic ratio (modified lines in/out) 0x46 0 1 1 0x0 0 0 dcu_m_lines_in 0x47 0 1 1 0x0 0 0 dcu_m_lines_out # L2 Cache # L1 side # events 0x28, 0x29, 0x2a, 0x2e, 0x22, 0x23 # memory side # events 0x21, 0x24, 0x25, 0x26, 0x27 -Label L2 cache instruction fetches per instruction retired 0x28 0 1 1 0xf 0 0 l2_ifetch 0xc0 0 1 1 0x0 0 0 inst_retired -Label L2 cache load requests per instruction retired 0x29 0 1 1 0xf 0 0 l2_ld 0xc0 0 1 1 0x0 0 0 inst_retired -Label L2 cache store requests per instruction retired 0x2a 0 1 1 0xf 0 0 l2_st 0xc0 0 1 1 0x0 0 0 inst_retired -Label L2 cache requests (L1 cache misses) per instruction retired 0x2e 0 1 1 0xf 0 0 l2_rqsts 0xc0 0 1 1 0x0 0 0 inst_retired -Label L1 to L2 fraction: instruction fetch / requests 0x28 0 1 1 0xf 0 0 l2_ifetch 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label L1 to L2 fraction: data load / requests 0x29 0 1 1 0xf 0 0 l2_ld 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label L1 to L2 fraction: data store / requests 0x2a 0 1 1 0xf 0 0 l2_st 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label Data busy fraction (data bus busy cycles per active cycle) 0x22 0 1 1 0x0 0 0 l2_dbus_busy 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label Data busy fraction (inbound data bus busy cycles per active cycle) 0x23 0 1 1 0x0 0 0 l2_dbus_busy_rd 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label L1 instruction-cache misses (lines in per fetch) 0x28 0 1 1 0xf 0 0 l2_ifetch 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label L1 instruction-cache misses (lines in per miss) 0x28 0 1 1 0xf 0 0 l2_ifetch 0x81 0 1 1 0x0 0 0 ifu_ifetch_miss -Label L1 instruction-cache misses (lines in per TLB miss) 0x28 0 1 1 0xf 0 0 l2_ifetch 0x85 0 1 1 0x0 0 0 itlb_miss -Label L2 cache traffic ratio (load/store) 0x29 0 1 1 0xf 0 0 l2_ld 0x2a 0 1 1 0xf 0 0 l2_st -Label L1 cache miss penalty (data bus busy cycles per L2 request) 0x22 0 1 1 0x0 0 0 l2_dbus_busy 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label L1 cache miss penalty (inbound data bus busy cycles per L2 request) 0x23 0 1 1 0x0 0 0 l2_dbus_busy_rd 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label Data bus traffic ratio (inbound cycles / total cycles) 0x23 0 1 1 0x0 0 0 l2_dbus_busy_rd 0x22 0 1 1 0x0 0 0 l2_dbus_busy -Label L2 cache misses per instruction retired 0x24 0 1 1 0x0 0 0 l2_lines_in 0xc0 0 1 1 0x0 0 0 inst_retired -Label L2 miss ratio 0x24 0 1 1 0x0 0 0 l2_lines_in 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label L2 cache traffic ratio (lines in/out) 0x24 0 1 1 0x0 0 0 l2_lines_in 0x26 0 1 1 0x0 0 0 l2_lines_out -Label L2 cache traffic ratio (lines in / modified lines in) 0x24 0 1 1 0x0 0 0 l2_lines_in 0x25 0 1 1 0x0 0 0 l2_m_lines_inm -Label L2 cache traffic ratio (modified lines in/out) 0x25 0 1 1 0x0 0 0 l2_m_lines_inm 0x27 0 1 1 0x0 0 0 l2_m_lines_outm -Label L2 cache traffic ratio (lines out / modified lines out) 0x26 0 1 1 0x0 0 0 l2_lines_out 0x27 0 1 1 0x0 0 0 l2_m_lines_outm -Label L1 / L2 fraction: lines in 0x45 0 1 1 0x0 0 0 dcu_lines_in 0x24 0 1 1 0x0 0 0 l2_lines_in -Label L1 / L2 fraction: modified lines in 0x46 0 1 1 0x0 0 0 dcu_m_lines_in 0x25 0 1 1 0x0 0 0 l2_m_lines_inm -Label L1 / L2 fraction: modified lines out 0x47 0 1 1 0x0 0 0 dcu_m_lines_out 0x27 0 1 1 0x0 0 0 l2_m_lines_outm -Label L2 cache address strobes per instruction retired 0x21 0 1 1 0x0 0 0 l2_ads 0xc0 0 1 1 0x0 0 0 inst_retired -Label L2 cache address strobes per L2 request 0x21 0 1 1 0x0 0 0 l2_ads 0x2e 0 1 1 0xf 0 0 l2_rqsts -Label L2 cache load requests per data reference 0x29 0 1 1 0xf 0 0 l2_ld 0x43 0 1 1 0x0 0 0 data_mem_refs -Label L2 cache load requests per L1 d-cache line in 0x29 0 1 1 0xf 0 0 l2_ld 0x45 0 1 1 0x0 0 0 dcu_lines_in -Label L1 d-cache modified lines in per L2 cache load request 0x46 0 1 1 0x0 0 0 dcu_m_lines_in 0x29 0 1 1 0xf 0 0 l2_ld # External Bus Logic # requests # events 0x60 # transactions # events 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70 # clocks # events 0x61, 0x62, 0x63, 0x64, 0x7a, 0x7b, 0x7e -Label External Bus, outstanding bus requests by L1 data load, per instruction retired 0x60 0 1 1 0x0 0 0 bus_req_outstanding 0xc0 0 1 1 0x0 0 0 inst_retired -Label External Bus, outstanding bus requests by L1 data load, per line allocated in L1 0x60 0 1 1 0x0 0 0 bus_req_outstanding 0x45 0 1 1 0x0 0 0 dcu_lines_in -Label External Bus, outstanding bus requests by L1 data load, per L1 miss outstanding 0x60 0 1 1 0x0 0 0 bus_req_outstanding 0x48 0 1 1 0x0 0 0 dcu_miss_outstanding -Label External Bus, outstanding bus requests by L1 data load, per L2 data load 0x60 0 1 1 0x0 0 0 bus_req_outstanding 0x29 0 1 1 0xf 0 0 l2_ld -Label External Bus, outstanding bus requests by L1 data load, per line allocated in L2 0x60 0 1 1 0x0 0 0 bus_req_outstanding 0x24 0 1 1 0x0 0 0 l2_lines_in -Label External Bus fraction: burst read / burst (this processor) 0x65 0 1 1 0x0 0 0 bus_tran_brd 0x6e 0 1 1 0x0 0 0 bus_tran_burst -Label External Bus fraction: burst read / burst (all agents) 0x65 0 1 1 0x20 0 0 bus_tran_brd 0x6e 0 1 1 0x20 0 0 bus_tran_burst -Label External Bus fraction: read-for-ownership / burst (this processor) 0x66 0 1 1 0x0 0 0 bus_tran_rfo 0x6e 0 1 1 0x0 0 0 bus_tran_burst -Label External Bus fraction: read-for-ownership / burst (all agents) 0x66 0 1 1 0x20 0 0 bus_tran_rfo 0x6e 0 1 1 0x20 0 0 bus_tran_burst -Label External Bus fraction: write-back / burst (this processor) 0x67 0 1 1 0x0 0 0 bus_trans_wb 0x6e 0 1 1 0x0 0 0 bus_tran_burst -Label External Bus fraction: write-back / burst (all agents) 0x67 0 1 1 0x20 0 0 bus_trans_wb 0x6e 0 1 1 0x20 0 0 bus_tran_burst -Label External Bus fraction: instruction fetch / burst (this processor) 0x68 0 1 1 0x0 0 0 bus_tran_ifetch 0x6e 0 1 1 0x0 0 0 bus_tran_burst -Label External Bus fraction: instruction fetch / burst (all agents) 0x68 0 1 1 0x20 0 0 bus_tran_ifetch 0x6e 0 1 1 0x20 0 0 bus_tran_burst -Label External Bus, instruction fetches per instruction retired 0x68 0 1 1 0x0 0 0 bus_tran_ifetch 0xc0 0 1 1 0x0 0 0 inst_retired -Label L2 instruction fetch miss ratio 0x68 0 1 1 0x0 0 0 bus_tran_ifetch 0x28 0 1 1 0xf 0 0 l2_ifetch -Label External Bus, instruction fetches per L1 i-cache fetch 0x68 0 1 1 0x0 0 0 bus_tran_ifetch 0x80 0 1 1 0x0 0 0 ifu_ifetch -Label External Bus fraction: partial write / partial (this processor) 0x6a 0 1 1 0x0 0 0 bus_tran_pwr 0x6b 0 1 1 0x0 0 0 bus_trans_p -Label External Bus fraction: partial write / partial (all agents) 0x6a 0 1 1 0x20 0 0 bus_tran_pwr 0x6b 0 1 1 0x20 0 0 bus_trans_p -Label External Bus fraction: burst / memory (this processor) 0x6e 0 1 1 0x0 0 0 bus_tran_burst 0x6f 0 1 1 0x0 0 0 bus_tran_mem -Label External Bus fraction: burst / memory (all agents) 0x6e 0 1 1 0x20 0 0 bus_tran_burst 0x6f 0 1 1 0x20 0 0 bus_tran_mem -Label External Bus fraction: partial / memory (this processor) 0x6b 0 1 1 0x0 0 0 bus_trans_p 0x6f 0 1 1 0x0 0 0 bus_tran_mem -Label External Bus fraction: partial / memory (all agents) 0x6b 0 1 1 0x20 0 0 bus_trans_p 0x6f 0 1 1 0x20 0 0 bus_tran_mem -Label External Bus fraction: invalidate / memory (this processor) 0x69 0 1 1 0x0 0 0 bus_tran_inval 0x6f 0 1 1 0x0 0 0 bus_tran_mem -Label External Bus fraction: invalidate / memory (all agents) 0x69 0 1 1 0x20 0 0 bus_tran_inval 0x6f 0 1 1 0x20 0 0 bus_tran_mem -Label External Bus fraction: memory / all transactions (this processor) 0x6f 0 1 1 0x0 0 0 bus_tran_mem 0x70 0 1 1 0x0 0 0 bus_tran_any -Label External Bus fraction: memory / all transactions (all agents) 0x6f 0 1 1 0x20 0 0 bus_tran_mem 0x70 0 1 1 0x20 0 0 bus_tran_any -Label External Bus fraction: I/O / all transactions (this processor) 0x6c 0 1 1 0x0 0 0 bus_trans_io 0x70 0 1 1 0x0 0 0 bus_tran_any -Label External Bus fraction: I/O / all transactions (all agents) 0x6c 0 1 1 0x20 0 0 bus_trans_io 0x70 0 1 1 0x20 0 0 bus_tran_any -Label External Bus fraction: deferred / all transactions (this processor) 0x6d 0 1 1 0x0 0 0 bus_tran_def 0x70 0 1 1 0x0 0 0 bus_tran_any -Label External Bus fraction: deferred / all transactions (all agents) 0x6d 0 1 1 0x20 0 0 bus_tran_def 0x70 0 1 1 0x20 0 0 bus_tran_any -Label Memory burst transactions per instruction retired 0x6e 0 1 1 0x20 0 0 bus_tran_burst 0xc0 0 1 1 0x0 0 0 inst_retired -Label External Bus partial transactions per instruction retired 0x6b 0 1 1 0x0 0 0 bus_trans_p 0xc0 0 1 1 0x0 0 0 inst_retired -Label Memory transactions per instruction retired 0x6f 0 1 1 0x20 0 0 bus_tran_mem 0xc0 0 1 1 0x0 0 0 inst_retired -Label External Bus transactions per instruction retired 0x70 0 1 1 0x20 0 0 bus_tran_any 0xc0 0 1 1 0x0 0 0 inst_retired -Label External Bus, driving DRDY (bus clocks by processor, processor clocks by any agent) 0x62 0 1 1 0x0 0 0 bus_drdy_clocks 0x62 0 1 1 0x20 0 0 bus_drdy_clocks -Label External Bus, driving DRDY (processor clocks by any agent per instruction retired) 0x62 0 1 1 0x20 0 0 bus_drdy_clocks 0xc0 0 1 1 0x0 0 0 inst_retired -Label External Bus, L1-L2 data bus vs. L2-memory external bus 0x22 0 1 1 0x0 0 0 l2_dbus_busy 0x62 0 1 1 0x20 0 0 bus_drdy_clocks -Label External Bus, processor receiving data, driving BNR pin (bus clocks) 0x64 0 1 1 0x0 0 0 bus_data_rcv 0x61 0 1 1 0x0 0 0 bus_bnr_drv -Label External Bus, processor receiving data (bus clocks) 0x64 0 1 1 0x0 0 0 bus_data_rcv 0x62 0 1 1 0x0 0 0 bus_drdy_clocks -Label External Bus, processor driving BNR pin (bus clocks) 0x61 0 1 1 0x0 0 0 bus_bnr_drv 0x62 0 1 1 0x0 0 0 bus_drdy_clocks -Label External Bus, asserting LOCK (processor clocks) 0x63 0 1 1 0x0 0 0 bus_lock_clocks 0x63 0 1 1 0x20 0 0 bus_lock_clocks -Label External Bus, processor driving HIT, HITM pins (bus clocks) 0x7a 0 1 1 0x0 0 0 bus_hit_drv 0x7b 0 1 1 0x0 0 0 bus_hitm_drv -Label External Bus, bus clock cycles during snoop stall 0x7e 0 1 1 0x0 0 0 bus_snoop_stall 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted # Memory Ordering # events 0x03, 0x04, 0x05 # # Segment Registers # events 0x06 # # Clocks # events 0x79 -Label Memory ordering, store buffer blocks (per data memory reference) 0x03 0 1 1 0x0 0 0 ld_blocks 0x43 0 1 1 0x0 0 0 data_mem_refs -Label Memory ordering, store buffer drain cycles (per block) 0x04 0 1 1 0x0 0 0 sb_drains 0x03 0 1 1 0x0 0 0 ld_blocks -Label Memory ordering, misaligned data memory references (per reference) 0x05 0 1 1 0x0 0 0 misalign_mem_ref 0x43 0 1 1 0x0 0 0 data_mem_refs -Label Segment register loads per instruction retired 0x06 0 1 1 0x0 0 0 segment_reg_loads 0xc0 0 1 1 0x0 0 0 inst_retired # Execution Units # # Floating-point # events 0x10, 0x11, 0x12, 0x13, 0x14, 0xc1 # Branches # events 0xe0, 0xe2, 0xe4, 0xe6, 0xc4, 0xc5, 0xc9, 0xca # Stalls # events 0xa2, 0xd2 -Label Floating-point operations executed per cycle 0x10 0 1 1 0x0 0 0 fp_comp_ops_exe 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label Floating-point operations executed; exceptions handled by microcode 0x10 0 1 1 0x0 0 0 fp_comp_ops_exe 0x11 0 1 1 0x0 0 0 fp_assist -Label Floating-point operations executed, multiply 0x10 0 1 1 0x0 0 0 fp_comp_ops_exe 0x12 0 1 1 0x0 0 0 mul -Label Floating-point operations executed, divide 0x10 0 1 1 0x0 0 0 fp_comp_ops_exe 0x13 0 1 1 0x0 0 0 div -Label Floating-point operations executed, divide unit busy, per divide 0x14 0 1 1 0x0 0 0 cycles_div_busy 0x13 0 1 1 0x0 0 0 div -Label Floating-point operations executed, divide unit busy, fraction 0x14 0 1 1 0x0 0 0 cycles_div_busy 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted -Label Branch frequency (branches decoded per instruction decoded) 0xe0 0 1 1 0x0 0 0 br_inst_decoded 0xd0 0 1 1 0x0 0 0 inst_decoder -Label Branch frequency (branches retired per instruction retired) 0xc4 0 1 1 0x0 0 0 br_inst_retired 0xc0 0 1 1 0x0 0 0 inst_retired -Label Mispredicted branches per instruction retired 0xc5 0 1 1 0x0 0 0 br_miss_pred_retired 0xc0 0 1 1 0x0 0 0 inst_retired -Label Branch speculation factor (branches decoded per branch retired) 0xe0 0 1 1 0x0 0 0 br_inst_decoded 0xc4 0 1 1 0x0 0 0 br_inst_retired -Label Branch Target Buffer miss ratio 0xe2 0 1 1 0x0 0 0 btb_misses 0xe0 0 1 1 0x0 0 0 br_inst_decoded -Label Branch mispredict ratio 0xc5 0 1 1 0x0 0 0 br_miss_pred_retired 0xc4 0 1 1 0x0 0 0 br_inst_retired -Label Branch taken ratio 0xc9 0 1 1 0x0 0 0 br_taken_retired 0xc4 0 1 1 0x0 0 0 br_inst_retired -Label Branch mispredict and taken ratio 0xca 0 1 1 0x0 0 0 br_miss_pred_taken_ret 0xc4 0 1 1 0x0 0 0 br_inst_retired -Label Speculated instructions per mispredicted branch 0xd0 0 1 1 0x0 0 0 inst_decoder 0xc5 0 1 1 0x0 0 0 br_miss_pred_retired -Label Branching: bogus branches, BACLEAR assertions 0xe4 0 1 1 0x0 0 0 br_bogus 0xe6 0 1 1 0x0 0 0 baclears -Label Partial RAT stalls per instruction retired 0xd2 0 1 1 0x0 0 0 partial_rat_stalls 0xc0 0 1 1 0x0 0 0 inst_retired # Interrupts # events 0xc6, 0xc7, 0xc8 -Label Cycles, interrupts are disabled, with pending interrupts 0xc6 0 1 1 0x0 0 0 cycles_int_masked 0xc7 0 1 1 0x0 0 0 cycles_int_pending_and_masked -Label Hardware interrupts received 0xc8 0 1 1 0x0 0 0 hw_int_rx 0x79 0 1 1 0x0 0 0 cpu_clk_unhalted # Pentium II only # MMX # events 0xb0, 0xb1, 0xb2, 0xb3, 0xcc, 0xcd, 0xce # Segments # events 0xd4, 0xd5, 0xd6 -Label MMX, instructions executed; saturating arithmetic instructions executed 0xb0 0 1 1 0x0 0 0 MMX_instr_exec 0xb1 0 1 1 0x0 0 0 MMX_sat_instr_exec -Label MMX, micro-operations executed; instructions executed 0xb2 0 1 1 0xf 0 0 MMX_uops_exec 0xb3 0 1 1 0x3f 0 0 MMX_instr_type_exec -Label MMX, transitions between FP and MMX 0xcc 0 1 1 0x0 0 0 fp_MMX_trans 0xcc 0 1 1 0x1 0 0 fp_MMX_trans -Label MMX, EMMS instructions executed; instructions retired 0xcd 0 1 1 0x0 0 0 MMX_assist 0xce 0 1 1 0x0 0 0 MMX_instr_ret -Label Segment register renaming stalls 0xd4 0 1 1 0xf 0 0 seg_rename_stalls 0x06 0 1 1 0x0 0 0 segment_reg_loads -Label Segment register renaming stalls per instruction retired 0xd4 0 1 1 0xf 0 0 seg_rename_stalls 0xc0 0 1 1 0x0 0 0 inst_retired -Label Segment register renames; segment register renames retired 0xd5 0 1 1 0xf 0 0 seg_reg_renames 0xd6 0 1 1 0x0 0 0 ret_seg_renames